FIG. 1 is a schematic view showing a conventional chip package structure in accordance with prior art. A conventional single-chip or multi-chip package structure is shown. The single-chip or multi-chip package structure 100 includes at least one chip 102, a plurality of structural material layers 104, a dielectric layer 106, a plurality of solder pads 107, and a metal layer 110. A plurality of solder pads 107 are disposed on the chip 102. A plurality of structural material layers 104 are connected to a lateral side of the chip 102, wherein the surface of the structural material layer 104 is aligned with the surface of the chip 102. The dielectric layer 106 is disposed on the structural material layer 104 and the chip 102, wherein the top surface of the surface of the chip 102 is aligned with the surface of the structural material layer 104. The dielectric layer 106 has a plurality of openings 108. The metal layer 110 is disposed on the dielectric layer 106 and the side-wall of the openings 108.
In order to increase the density of electrical connections of the package structure, a through molding compound technology is typically applied to the structural material layer 104 first, such as mechanical drilling through the structural material layer 104 to enable electrical connectivity to the metal layer 110. However, at present, the through molding compound technology is costly.